chipgallery.blogspot.com

Chip Gallery

Friday, February 08, 2013. 原田 LEAP LPT4S SC16. Posted by Masanori Hashimoto @ 2:16 PM. Posted by Masanori Hashimoto @ 2:15 PM. 大政 VDEC 2012/10/10 TO. Posted by Masanori Hashimoto @ 2:15 PM. Posted by Masanori Hashimoto @ 2:14 PM. 天木、原田 TED 2012/8 TO. Posted by Masanori Hashimoto @ 2:14 PM. Posted by Masanori Hashimoto @ 2:13 PM. Dawood, 郡浦 VDEC 2012/4/4 TO. Posted by Masanori Hashimoto @ 2:11 PM. Dawood, 郡浦 VDEC 2012/2/22 TO. Posted by Masanori Hashimoto @ 2:11 PM. プロセス: 65nm CMOS 12層配線プロセス (VDEC). ーティ比調...

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Friday, February 08, 2013. 原田 LEAP LPT4S SC16. Posted by Masanori Hashimoto @ 2:16 PM. Posted by Masanori Hashimoto @ 2:15 PM. 大政 VDEC 2012/10/10 TO. Posted by Masanori Hashimoto @ 2:15 PM. Posted by Masanori Hashimoto @ 2:14 PM. 天木、原田 TED 2012/8 TO. Posted by Masanori Hashimoto @ 2:14 PM. Posted by Masanori Hashimoto @ 2:13 PM. Dawood, 郡浦 VDEC 2012/4/4 TO. Posted by Masanori Hashimoto @ 2:11 PM. Dawood, 郡浦 VDEC 2012/2/22 TO. Posted by Masanori Hashimoto @ 2:11 PM. プロセス: 65nm CMOS 12層配線プロセス (VDEC). ーティ比調...

<META> KEYWORDS

1 chip gallery

2 2004年以降に試作してきたチップを紹介します

3 leap lpt 4s sc08

4 原田 leap lpt 3

5 チップサイズ 2mmx2mm

6 トランジスタ数

7 ゲート数

8 設計者天木君、橋本

9 題目耐環境変動オシレータベース真性乱数生成回路の試作２

10 さらに、ゆらぎ量低下を検知するためのゆらぎモニタを実装した

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chip gallery,2004年以降に試作してきたチップを紹介します,leap lpt 4s sc08,原田 leap lpt 3,チップサイズ 2mmx2mm,トランジスタ数,ゲート数,設計者天木君、橋本,題目耐環境変動オシレータベース真性乱数生成回路の試作２,さらに、ゆらぎ量低下を検知するためのゆらぎモニタを実装した,設計担当者天木君、原田君、橋本,題目天木分耐環境変動オシレータベース真性乱数生成回路の試作１,物理乱数生成器,設計者天木君、高井君、橋本,設計者原田君、橋本,チップ概要

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Chip Gallery | chipgallery.blogspot.com Reviews

https://chipgallery.blogspot.com

Friday, February 08, 2013. 原田 LEAP LPT4S SC16. Posted by Masanori Hashimoto @ 2:16 PM. Posted by Masanori Hashimoto @ 2:15 PM. 大政 VDEC 2012/10/10 TO. Posted by Masanori Hashimoto @ 2:15 PM. Posted by Masanori Hashimoto @ 2:14 PM. 天木、原田 TED 2012/8 TO. Posted by Masanori Hashimoto @ 2:14 PM. Posted by Masanori Hashimoto @ 2:13 PM. Dawood, 郡浦 VDEC 2012/4/4 TO. Posted by Masanori Hashimoto @ 2:11 PM. Dawood, 郡浦 VDEC 2012/2/22 TO. Posted by Masanori Hashimoto @ 2:11 PM. プロセス: 65nm CMOS 12層配線プロセス (VDEC). ーティ比調...

INTERNAL PAGES

chipgallery.blogspot.com

1

Chip Gallery: 試作チップ33(65nm)

http://www.chipgallery.blogspot.com/2013/02/3465nm.html

Friday, February 08, 2013. Posted by Masanori Hashimoto @ 2:14 PM. View my complete profile.

2

Chip Gallery: 試作チップ21(65nm)

http://www.chipgallery.blogspot.com/2013/02/2165nm.html

Friday, February 08, 2013. プロセス: 65nm CMOS 12層配線プロセス. 概要本試作では，試作チップ18の放射線起因一過性パルス(SET)のパルス幅測定回路を改善し，製造ばらつきや負バイアス温度不安定性(NBTI)によるパルス幅変動の除去と高いSETターゲット面積効率の実現を目的とした試作回路では，10段のインバータチェインを並列化したものを1個のパルス幅測定回路に収束することで，高いターゲット回路面積を実現したまた，SETの伝播経路によるパルス幅の変動を校正するための校正機構を実装した試作チップを用いて中性子照射実験を実施し，SETのパルス幅分布を取得可能であることを確認したまた，回路の校正によりチップ間/チップ内製造ばらつきがパルス幅測定にとって無視できないものであることを確認した. Posted by Masanori Hashimoto @ 2:04 PM. View my complete profile.

3

Chip Gallery: 試作チップ28(65nm)

http://www.chipgallery.blogspot.com/2013/02/2965nm.html

Friday, February 08, 2013. プロセス: 65nm CMOS 12層配線プロセス (VDEC). 提案するデューティ比自動調整機構により、温度を 5 60 と変化させた場合の `1' 出現確率変動量を 0.90 [%] から 0.05 [%]に低減できることを確認した。これは、NIST Frequency test に合格するのに十分な低減効果である。また、デューティ比モニタは、ランダムサンプリング法を用いたデューティ比推定方法と比較して 3,500 倍高速にデューティ比を推定可能であることを確認した。 Posted by Masanori Hashimoto @ 2:10 PM. View my complete profile.

4

Chip Gallery: 試作チップ29(65nm)

http://www.chipgallery.blogspot.com/2013/02/3065nm.html

Friday, February 08, 2013. Dawood, 郡浦 VDEC 2012/2/22 TO. Posted by Masanori Hashimoto @ 2:11 PM. View my complete profile.

5

Chip Gallery: 試作チップ17(65nm)

http://www.chipgallery.blogspot.com/2010/04/1765nm.html

Friday, April 02, 2010. プロセス: 65nm CMOS 12層配線プロセス. Posted by Masanori Hashimoto @ 8:37 PM. View my complete profile.

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researchactivities.blogspot.com

Research Activities: IEICE VLD Excellent Student Author Award

http://researchactivities.blogspot.com/2015/03/ieice-vld-excellent-student-author-award.html

Thursday, March 05, 2015. IEICE VLD Excellent Student Author Award. M2の飯塚翔一君がIEICE VLD Excellent Student Author Awardを受賞しました。那覇市で開催されたVLD研究会において記念講演を行いました(2015/3/3)。 Area Efficient Device-Parameter Estimation using Sensitivity-Configurable Ring Oscillator". IEICE VLD Excellent Student Author Award. View my complete profile.

researchactivities.blogspot.com

Research Activities: March 2014

http://researchactivities.blogspot.com/2014_03_01_archive.html

Saturday, March 08, 2014. 大阪市立大学で開催された電子情報通信学会CAS研究会にて M1 鵜川翔平君が日頃の研究成果を発表しました(2014/3/7)．カリフォルニア州サンタクルーズで開催された TAU 2014 でM2の上野美保さんが研究成果を発表しました(2014/3/7)。 Trace-based fault localization with supply voltage sensor". 2013年3月に博士後期課程を修了した天木健彦君(写真左から5番目)、2014年3月に博士後期課程を修了予定の原田諒君(右から4番目)がIEEE関西支部より、学生研究奨励賞を受賞しました。それぞれ、IEEE Transactions on Information Forensics and Security, IEEE Transactions on Nuclear Scienceの論文誌掲載による受賞です。おめでとう。(2014/2/17). 無事、卒業論文を書き上げ、発表を終えました(2014/2/17)。 Subscribe to: Posts (Atom).

researchactivities.blogspot.com

Research Activities: October 2014

http://researchactivities.blogspot.com/2014_10_01_archive.html

Friday, October 24, 2014. アメリカワシントン州シアトルで開催された International Test Conference (ITC) 2014. において、卒業した上野美保さんの研究成果をポスター発表しました(2014/10/22)。また、橋本はITC 2014のプログラム委員であり、セッションチェアを務めました。 Real-Time Supply Voltage Sensor for Trace-based Fault Localization". Tuesday, October 14, 2014. Toward Robust Subthreshold Circuit Design: Variability and Soft Error Perspective". Subscribe to: Posts (Atom). View my complete profile.

researchactivities.blogspot.com

Research Activities: June 2015

http://researchactivities.blogspot.com/2015_06_01_archive.html

Thursday, June 25, 2015. JST CRESTの成果である以下の論文に対して、電子情報通信学会リコンフィギャラブルシステム研究会より優秀リコンフィギャラブルシステム論文賞を授与頂きました(2015/6/19)。 Subscribe to: Posts (Atom). View my complete profile.

researchactivities.blogspot.com

Research Activities: February 2015

http://researchactivities.blogspot.com/2015_02_01_archive.html

Saturday, February 07, 2015. Prof Li Jiang 来訪. 中国の上海交通大学のProf. Li Jiang が研究室を訪問しました。講演を行って頂くとともに、研究ディスカッションを行いました(2015/1/23)。 Fault tolerance for 2.5D/3D ICs". 幕張で開催されたAsia and South Pacific Design Automation Conference (ASP-DAC) において、M2の飯塚君が研究成果の発表を行いました(2015/1/22)。 Area Efficient Device-Parameter Estimation Using Sensitivity-Configurable Ring Oscillator". University Design Contest において、卒業した天木君、郡浦君、Dawood君の研究成果の発表を橋本が発表しました(2015/1/20)。 Subscribe to: Posts (Atom). Prof Li Jiang 来訪.

researchactivities.blogspot.com

Research Activities: December 2014

http://researchactivities.blogspot.com/2014_12_01_archive.html

Tuesday, December 02, 2014. Subscribe to: Posts (Atom). View my complete profile.

researchactivities.blogspot.com

Research Activities: March 2015

http://researchactivities.blogspot.com/2015_03_01_archive.html

Thursday, March 26, 2015. を受賞し、表彰式が行われました(2015/3/25)。おめでとう。博士前期課程での学業、研究が評価され、M2の飯塚翔一君が大阪大学情報科学研究科賞を受賞しました。おめでとう。今後の活躍を期待しています。(2015/3/25). 上村大樹さんが2015/3/25付けで学位(大阪大学博士(情報科学) を授与されました。おめでとうございます。特にマイクロプロセッサのソフトエラー対策に取り組み、多くの対策技術と解析技術を開発するとともに、IEEE Trans. Nuclear Science等に多くの論文を発表され、学位を取得されました。本業が忙しい中、学会発表と博士論文を執筆し、1年半での短縮卒業、すばらしいペースでした。今後の益々のご活躍を祈念いたします。 A Study on Soft Error Mitigation for Microprocessor in Bulk CMOS Technology". Wednesday, March 18, 2015. Thursday, March 05, 2015.

researchactivities.blogspot.com

Research Activities: November 2014

http://researchactivities.blogspot.com/2014_11_01_archive.html

Wednesday, November 26, 2014. 沖縄県石垣市で開催されたAsia Pacific Conference on Circuits and Systems (APCCAS) 2014 において、橋本が招待講演を行いました(2014/11/20)。本特別セッションは橋本が企画しました。 Stochastic Verification of Run-time Performance Adaptation with Field Delay Testing". Wednesday, November 19, 2014. 中国の杭州で開催された Asian Test Symposium (ATS) 2014 において、橋本が招待講演を行いました(2014/11/18)。 Opportunities and Verification Challenges of Run-time Performance Adaptation". Subscribe to: Posts (Atom). View my complete profile.

researchactivities.blogspot.com

Research Activities: August 2014

http://researchactivities.blogspot.com/2014_08_01_archive.html

Friday, August 29, 2014. 岐阜県の下呂温泉で開催されたDAシンポジウム2014でM2の飯塚翔一君, M1の増田豊君が研究成果を発表をしました(2014/8/29)。韓国太田市のDaejeon Convention Centerで開催されたEDA Workshop 2014において、橋本が研究成果の発表を行いました(2014/8/26)。 Stochastic Error Rate Estimation for Adaptive Speed Control with Field Delay Testing". National Taiwan University (国立台湾大学) 訪問. Run-time Performance Adaptation with Field Delay Testing – How can we verify in design time? Thursday, August 28, 2014. National Cheng Kung University (国立成功大学) 訪問. Saturday, August 02, 2014. フランスのパリで...

researchactivities.blogspot.com

Research Activities: IEEE VR 2015

http://researchactivities.blogspot.com/2015/03/ieee-vr-2015.html

Thursday, March 26, 2015. フランスのアルル市で開催された IEEE Virtual Reality (VR) において、M2の鵜川君が研究成果をポスター発表しました(2015/3/25)。 3D Node Localization from Node-to-Node Distance Information using Cross-Entropy Method". IEICE VLD Excellent Student Author Award. View my complete profile.

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Friday, February 08, 2013. 原田 LEAP LPT4S SC16. Posted by Masanori Hashimoto @ 2:16 PM. Posted by Masanori Hashimoto @ 2:15 PM. 大政 VDEC 2012/10/10 TO. Posted by Masanori Hashimoto @ 2:15 PM. Posted by Masanori Hashimoto @ 2:14 PM. 天木、原田 TED 2012/8 TO. Posted by Masanori Hashimoto @ 2:14 PM. Posted by Masanori Hashimoto @ 2:13 PM. Dawood, 郡浦 VDEC 2012/4/4 TO. Posted by Masanori Hashimoto @ 2:11 PM. Dawood, 郡浦 VDEC 2012/2/22 TO. Posted by Masanori Hashimoto @ 2:11 PM. プロセス: 65nm CMOS 12層配線プロセス (VDEC). ーティ比調...

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